Solid state multi-layer avalanche diodes, such as silicon or gallium arsenide IMPATT diodes for example, have been used for several years in the microwave industry as active semiconductor devices in microwave oscillators and amplifiers. To a first order approximation, the operational frequency, f, in GHz of these diodes, e.g. single-drift-region IMPATT diodes, is related to the width, W, in micrometers, of the intermediate P or N type layer of three layer avalanche diodes as follows: EQU f(GHz) = 30/W (.mu.m) Equation (Eq.) 1
In the construction of microwave oscillators and amplifiers, it has been one practice to mount these semiconductor diodes on one surface of a waveguide cavity and thereafter make DC electrical contact to these diodes using a pin or post-like connection. Such contact is necessary to supply the diodes with appropriate DC operating bias for oscillation or amplification of microwave energy.
As the maximum operating frequency requirements for these semiconductor diodes were increased, especially with the interest in increasing the operational frequency of solid state oscillators and amplifiers into the millimeter wavelength range, it became necessary to reduce the geometry of these diodes, e.g. IMPATT diodes, to produce a corresponding reduction in the width of the P and N type layers forming the diodes, as specified by Eq. 1. This requirement for reducing the geometry of these solid state diodes obviously produced a corresponding reduction in their structural strength and ability to withstand contact pressures, such as the contact pressures produced when a DC bias pin is brought directly into contact with one surface of the diode.
To alleviate the latter problem, workers in this art began to mount the diodes in a manner that would eliminate the requirement for directly contacting one surface of the diode with the DC bias pin. One of the approaches used to accomplish this involved mounting one surface of the diode on a conducting substrate forming part of an insulating package and extending a conductive ribbon from the tab of the vertical insulator down into electrical contact with the second surface of the diode. Now the upper portion of the package could be utilized for making direct pressure contact to a DC bias pin, and the diode itself was removed from any direct pressure from such a pin. This type of package structure is disclosed, for example, in an article by N. B. Kramer entitled "IMPATT Diodes and Millimeter Wave Applications Grow Up Together" Electronics, Oct. 11, 1971, at page 79.
The electrical characteristics of the above and other similar packaging techniques can be represented by a lumped element equivalent circuit of parasitics near the active diode. In the simplest form, this parasitic equivalent circuit consists of a lead inductance in series with the active diode, and this series combination is shunted by a parallel combination of a conductance, G, and capacitance, C, of the remainder of the package. Thus, the total parasitic equivalent capacitance C and inductance L causes the package to have a natural resonant frequency f.sub.pack, which is inversely proportional to the square root of LC, that is: EQU f.sub.pack .varies. 1/.sqroot.LC Equation (Eq.) 2
The above-described package must not only provide an arrangement to remove mechanical pressure from the diode as mentioned, but the electrical properties of the package must be such that they do not greatly detract from the interaction between the diode and the microwave cavity in which the diode is mounted. This is accomplished by making G small to reduce the conductance loss of the package, and by either making f.sub.pack much higher than the operating frequency f of the diode (minimizing the impedance transformation from the diode chip to the package terminals) or by making f.sub.pack close to the operating frequency of the cavity in order to use the package transformation as part of the diode/waveguide impedance matching network. However, at frequencies .gtorsim. 100 GHz, the parasitic inductance and capacitance associated with these packages produces a natural resonance f.sub.pack which is below the desired operation frequency, making it difficult to realize the proper device circuit interaction. In any event, it is desirable from the point of view of circuit design to provide a package arrangement with reproducible parasitics so that the circuit configuration can be designed to compensate for these parasitics as much as possible.
Another difficulty that arises in the construction of diodes for operation above 100 GHz is the mechanical damage that occurs to the diode during the fabrication of the package arrangement. That is, the size (area) of these diodes becomes reduced to such an extent that the strength of the metal contact bond to the diode is weakened and contact bonding failures often occur.
In the fabrication of high frequency semiconductor devices of the type described, it is also important to control the DC electrical characteristics for optimum device performance. A feature common to certain such device structures formed with a mesa geometry is the exposure of their p-n junctions to an uncontrolled environment. The electrical characteristics of these devices, notably the reverse-bias leakage currents associated with exposed or unpassivated junctions, are more difficult to control when compared to junctions that are passivated. It is desirable, therefore, to develop a package arrangement that not only has mechanical strength and low-losses at high frequencies, but one that also provides complete passivation of the p-n junction.
One prior art approach for fabricating semiconductor devices that have uniform avalanche breakdown junction characteristic of mesa device structures while providing the desirable junction passivation is described in a U.S. Pat. No. 3,649,386 issued to B. T. Murphy. In Murphy's approach, a dielectric layer, such as silicon dioxide, is formed around the edges of the mesas, so that the top surface of the dielectric layer is substantially coplanar with the top surfaces of the individual semiconductor mesas. This oxide provides surface passivation of the p-n junction as well as structural support for the mesas in a subsequent contact bonding operation. The silicon dioxide dielectric has a low conductance G and thus produces a minimum amount of resistive loss at high frequencies. To minimize the parasitic inductance L associated with this planar-mesa package, the top and bottom surface of the planarized mesas can be bonded directly to layers of contact and heat sink metallization. Such metallization completes the package for the diode, and the top and bottom metal surfaces of the above package may be contacted directly to a DC bias pin in a microwave cavity or the like.
The above planar-mesa approach to semiconductor diode packaging has, however, several distinct disadvantages, among which include the difficulty in adjusting the oxide thickness to the exact height of the mesa in order to obtain an oxide surface which is coplanar with the mesa height. Additionally, the high temperatures necessary for the thermal oxide growth cause a significant diffusion of the previously established doping profiles, resulting in degradation of device performance.
When Murphy's approach in U.S. Pat. No. 3,649,386 to junction passivation is combined with an additional etching step that produces another mesa in the oxide surrounding the previously formed semiconductor mesa, a passivated structure is formed that can be directly bonded to a heat sink, as described in U.S. Pat. No. 3,896,478 by R. Henry. The major disadvantage of this approach for high frequency devices designed to operate at millimeter-wavelengths is the large shunting reactance associated with the thin silicon dioxide layer that surrounds the p-n junction of the semiconductor mesa. Furthermore, reduction to practice of structures similar to the one purposed by Henry necessitates several complicated processing steps that result in low device yields.
Another approach for fabricating passivated semiconductor diodes of the general type described without requiring ribbon bonding and its associated housing support members is described in U.S. Pat. No. 3,558,366 to M. P. Lepselter. Lepselter's approach is to bombard selected regions of a silicon crystal with gold ions in order to raise the resistivity of the silicon crystal around the active diode regions therein. The Lepselter approach has several disadvantages, among which include the very high acceleration energies necessary to accelerate gold ions (of heavy mass) to the required depth into the silicon crystal. Other disadvantages of the Lepselter approach include the requirement for accelerating these gold ions through an oxide layer on the surface of the silicon crystal and also the ion implantation damage to the silicon crystal; in Lepselter's process this damage must either go unannealed in the fabrication of the ultimate device structure, or if annealed the annealing temperatures produce significant lateral and horizontal diffusion of the implanted gold ions, which result in either degradation or destruction of the device's PN junction geometry and performance.
Another prior art approach to fabricating devices of the general type described herein is disclosed in an article by Foyt et al entitled "Isolation of Junction Devices in GaAs Using Proton Bombardment" in Solid-State Electronics, vol. 12, 1969, pp. 209-214. In the above Foyt et al process, protons are utilized to bombard and raise the resistivity of certain layers of gallium arsenide IMPATT diodes in order to define the active device region of these structures and provide passivation therefor. By using proton bombardment, the Foyt et al approach does not require the high acceleration potentials required in the above Lepselter approach. But the Foyt et al approach, like the Lepselter approach, produces an ultimate device structure in which proton bombarded high-resistivity (semi-insulating) regions must necessarily be unannealed, thereby leaving the semiconductor crystal damaged in that portion of the structure bombarded by protons and immediately surrounding the active device regions of the diode structure.
Thus, the above-described Foyt et al and Lepselter approaches are similar in that both of these processes first introduce conductivity type determining impurities into the semiconductor crystal to establish the doping profiles of the active device regions and define the PN junctions therein, and thereafter utilize particle bombardment and implantation to control the exact geometry and current limiting necessary for the active device regions. Thus, this prior art sequence of processing steps leaves the particle bombardment damage present in the ultimate device structure.
Summarizing, therefore, in all of the Lepselter, Foyt et al and planar-mesa approaches described above, the impurity concentration and PN junctions for the active device regions are formed first, and thereafter geometry control, passivation and current limiting for these regions (and PN junctions) are provided last. Obviously, any attempt to anneal the semiconductor structures thus formed and remove implantation damage after completion of these implantation steps would adversely lower the resistivity of the semiconductor crystal which was intentionally raised by ion implantation in the first place. Although the passivation feature is retained in these approaches, the lower resistivity of the semiconductor leads to significant degradation of the microwave characteristics of the active device. And if annealing is attempted in the Lepselter approach described above, significant degradation of the active PN junction area is produced by the above-described enhanced diffusion effects.